Nicholas Collins

(602) 284-6425

Phoenix, AZ

Objective:

Searching for a consulting position performing digital ASIC design and/or verification.

Academic Background:

Louisiana State University: BSEE, June 1996.

Expertise Summary:

System Verilog, Verilog, VHDL
Perl scripting
System Verilog OVM class from Mentor Graphics
Cadence NC-Verilog, MTI ModelSim and VCS simulators
Spyglass, VNavigator, Cadence Virtuoso and Hierarchy Editor

Experience:

Intel Corp -- Feb ‘08 to Sept `08 Chandler, AZ

As a consulting engineer, provided verification services for developing SOC with embedded Intel processor. Worked in System Verilog AVM environment writing sims for Intel DFT logic and for Clock/Reset logic of SOC. Also helped in verifying CPU-related sims with Intel cosimulation tool (DVT) to communicate between VCS and ModelSim simulators. Afterwards, I initiated conversion flow of SOC RTL cosimulation from mixed-sim to entirely VCS.

Qualcomm Inc – Sep ‘07 to Jan ‘08 Chandler, AZ

As a consulting engineer, provided design and verification services on mixed-signal power management IC. Designed RTL for OTP memory controller with SPI interface. Created verilog models for analog portions of design from Cadence schematics and designer feedback. Wrote testbench using System Verilog and debugged top-level sims using VCS.

Intel Corp -- Oct ‘05 to Apr ‘06 Chandler, AZ

As a consulting engineer, provided verification services for developing a Network Processor SOC. Primarily focused on Gigabit Ethernet controller performing RTL and gate-level simulations. Performed code coverage using VNavigator and MTI. Responsible for identifying and resolving various bugs found in the design and testbench. Created random simcases which performed exhaustive testing and was also leveraged for functional coverage. Test environment included configurations for speed, duplex and mode (MII, GMII, TBI). Randomized various aspects of IEEE 802.3 such as: extend packets, address filtering, descriptor tables, IFG, PAUSE. Also verified seperate unit performing RGMII translation.

Canesta Inc – Feb ‘05 to May ‘05 Sunnyvale, CA

As a consulting engineer, provided design and verification services for 3D-imaging ASIC using VHDL with ModelSim simulator. Wrote RTL for Serial Peripheral Interface (SPI), DMA interface and other internal sub-designs. Created verification infrastructure for block-level and top-level sims using VHDL and C-shell scripts. Wrote Perl scripts to generate random data for RAM simulations in VHDL. Debugged gate-level netlist and SDF problems in GLS.

Intel Corp -- Aug ‘03 to Aug ‘04 Chandler, AZ

As a consulting engineer, provided verification services for developing a 1.2M AFE-Baseband SOC design. Designed baseband signalling and bus interface block. Contributed to full-chip integration. Developed self-checking, block-level and top-level Verilog sim cases. Modularized common testbench interfaces into transactors (BFMs) that can be used in block-level and top-level sims. Created scripts for simulation regressions using MTI and VCS simulators. Generated EVCD vectors for IMS lab testing.

Bandspeed Inc -- July ‘02 to Dec ‘02 Austin, TX

As a consulting engineer, provided verification services for developing an Ethernet switch design. Developed Verilog functional models for the external Ethernet MII interface. Also, created internal bus interface models for block-level simulations. These Verilog models included self-checking tasks/functions to simplify writing simcases. Responsible for writing and debugging dozens of block-level sims for two major blocks.

Intel Corp –- July ‘00 to Oct ‘01 Sacramento, CA

As a consulting engineer, provided verification services for developing a Gigabit PHY core. Helped integrate this PHY into a four-port Gigabit Ethernet transceiver ASIC and also participated in its RTL verification. Other tasks involved helping create and maintain the simulation environment, which consisted of multiple interactive probes for transmitting and receiving 10/100, GMII and SGMII packets. Debugged and corrected many problems within sim environment and design. Responsible for writing and debugging many top-level sims in Verilog. Wrote Verilog behavioral models for analog portions for simulation purposes.

Intel Corp -- Nov ‘99 to June ‘00 Sacramento, CA

As a consulting verification engineer, used MTI simulator and developed VHDL sims for verifying multiport Ethernet 10/100 transceiver. Most simulations written specifically for RMII interface of ASIC, such as reception and transmission of packets, FIFO operation, and out-of-band signaling.

Level One Comm. –- Sept ‘99 to Nov ‘99 Sacramento, CA

As a consulting engineer, integrated IP switch core with eight 10/100 PHYs for an 8-port Ethernet switch ASIC. This involved pad instantiation, testmode configuration, and pin multiplexing. Interfaced with synthesis team. Verified RTL and gate-level non-functional sims such as NAND tree, BIST, and scan tests.

Level One Comm. –- March ‘99 to April ‘99 Sacramento, CA

As a consulting engineer, developed VHDL and Verilog test environments for serial controller design coded in VHDL. Test environment included memory, test cases, procedures, and pad module. Used InterHDLs VHDL/Verilog translator to convert design into Verilog. Used MTI simulator for functional verification. Also helped to integrate this serial controller design into another ASIC.

SmartSand Consulting -- Oct ‘98 to Feb ‘99 Sunnyvale, CA

Consultant to fabless semiconductor company. Designed high-speed SONET application to multiplex four STS-12 frames into single STS-48 frames. This involved calculations for J0/Z0 bytes, B1 bytes, M1 bytes and B2 bytes. Coded in Verilog HDL and simulated using VSIM and Undertow simulation tools.

Consultant to IP core company. Verified PCI core using Verilog and Polaris simulation tools. Tested various functions of the PCI, such as configuration, interface control, error reporting, dual-addressing, and special cycles.

Lockheed Martin -- June ‘96 to Aug ‘98 Sunnyvale, CA

Served as ASIC Design Engineer on 72k-gate, radiation-hard, attitude control and telemetry interface ASIC. Coded design in VHDL and simulated using Synopsys VSS. Synthesized design using Synopsys. Inserted internal scan chains and created ATPG vectors using Synopsys Test Compiler. Performed static-timing analyses using Synopsys DesignTime. Performed gate-level verification by vector comparison. Converted functional and ATPG vectors into foundry-specific format using VTRAN translation tool. Used QuickTurn emulator to debug board/ASIC issues prior to tape-out.