· Currently, member of the Strong Arm 2 (SA2) design Group

INTEL CORPORATION, Chandler, AZ December 2007 to July 2008

Worked as Mix-Signal circuit designer and validation consultant in Intel’s New Business Initiatives developed high-speed (25-50MHz) multi-phase PC voltage regulator ICs in an Intel 0.13uM process. Responsibilities included:

· Supported the 10-bit R-String DAC design to use in control loop path.

· Developed Verilog, Verilog-AMS and Verilog-A models for Block-level and Top-level validation.

· Developed and Supported Chip-level validation test-benches and Behavioral models for Top-level validation simulations both Mixed-mode (Cadence AMS) and transistor level.

FreeScale Semiconductors, Chandler, AZ March, 2005 to August 2007

· Worked on Phase Interpolator for 5Gbits/s Serial I/O using 65nm CMOSSOI technology. This was a newly developed architecture; responsibilities include: design a family of Current Mode Logic (CML) circuits such as Buffers, Latch & Flip-Flops; bias circuit and the Phase Interpolator.

· Supported the design of DLL circuit (1.25GHz) for the Serial I/O; responsibilities included redesigning some components of the DLL circuit, circuit simulation, supervising layout, validation and verification.

· Support and delivery of a Phase Interpolator Design for the 1.25Gb/s Serial I/O; responsibilities included circuit simulations, layout supervision, validation and verification.

INTEL CORPORATION, Chandler, AZ June, 1997 to February 2005

· Design/Implementation/Validation & Verification of a 14-bit resistor string DAC to use as Automatic Frequency Control (AFC) DAC for the GSM/GPRS chipset. Validated all my units from the top level using VCS/NANOSIM.

· Design/Implementation/Validation & Verification of a 6-order Biquad Low-Pass Filter to control the power level of the off-chip power amplifier.

· Designed a control ADC (Cyclic architecture) for the CDMA chipset product. Tasks included the design of OTA, sample-and-hold amplifier, comparator, clock generation and digital decoding logic, layout supervision, and silicon debug and characterization.

· Designed Clock-Reset unit for the Intel Xscale Microprocessor. Tasks included, custom Logic Design, RTL, layout supervision, silicon debug and characterization of the PLL circuit and Clock-Reset unit.

· Chip level mix-signal Validation & Verification, developed behavioral models using VHDL and Saber MAST language for validation & verification of the image sensor chip.

Arizona State University, Tempe, AZ August, 1996 to June 1997

Graduate Research Assistant for Electronic Packaging lab

1. Modeled an Analog-to-Digital Converter module using Saber’s MAST language and MagiCAD.

2. Assisted with design of Mixed-signal models using Saber’s MAST language.

3. Created a Signal-Integrity template for high-speed systems using Saber’s MAST language.

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