Jason Graalum

Objective

Use my broad range of EDA skills and experiences promoting and advancing design automation tools and flows

Summary

§  Consulted with new silicon foundry company regarding development and customer support of advanced process node PDK

§  Design Package Lead responsible for program management and quality assurance of PDK and design flow development for 80nm and 35nm CMOS process nodes

§  CAD Team Lead responsible for development and support of full range of Back-End design tools and libraries

§  Simulation Team Lead responsible for development and implementation of large-D/large-A mixed signal simulation environment

§  Verification Engineer/Manager responsible for developing full-custom fullchip simulation methodology and environment using Verilog gate-level/primitive element netlists and behavioral models of analog circuits

Core Competencies

§  Extensive PDK Development and Program Management Experience

§  Design Automation Methodology Development and Deployment

§  Hands-on Verification Environment and Infrastructure Development and Management

§  Integrated Circuit Physical Verification Development

§  Logic and Analog Block Behavioral Modeling and Verification

§  Custom Gate-Level Timing and Cell Characterization

§  EDA Tool Development and Use: NCVerilog(Incisive Unified Simulator), Nanosim, Discovery AMS, Hercules DRC/LVS, STAR-RC, Cadence DFII Environment, Synchronicity DesignSync/DFIISync/ProjectSync

§  Languages: Perl, Verilog, SystemVerilog, Skill, C, Tcl, C-Shell

§  Windows Tools: Microsoft Productivity Tools

§  Unix/Linux Tools: CVS, Subversion, Platform Computing LSF

§  Excellent short-term(support) versus long-term(development) goal management

§  Issue resolution – inter-team and intra-team conflicts

§  Cross-functional team organization

§  Effective remote team supervision

§  Experienced technical trainer and mentor

 

 

 

 

 

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Professional Experience

2009-          GLOBALFOUNDRIES                                                                  Sunnyvale, California

                     Design Enablement Consultant– 28nm ASIC Foundry

§  Contributed to the creation of the Design Enablement organization chartered with the development and customer support of advanced process node PDKs

§  Provided direct on-site customer support for PDK deployment, evaluation, and qualification

§  Assisted senior management by creating and facilitating an aggressive hiring plan

§  Provided consulting to PDK Development and QA teams to develop a leading edge environment for the creation and support of high quality PDK components

2007-2009 Qimonda AG                                                                                    Munich, Germany

                     Design Platform Leader – 80nm DRAM Foundry

§  Coordinate between business unit management, EDA experts, and design management during development of design methodology, design flow, and required IP

§  Develop design PDKs and design flows required for full-custom circuit design and layout

§  Visit customer sites in support of PDK and design flow promotion and deployment

Design Platform Leader – 35nm process node

§  Provide technical leadership to EDA tool experts during PDK and design flow development

§  Act as technical interface between process development, design, and EDA development teams during the process node development phase and initial design tapeout

2002-2007    Micron Technology, Inc.                                                                  Boise, Idaho

                     CAD Methodology Manager

§  Manage team of Senior CAD and Senior Design Engineers tasked with the development and proto-typing of advanced design automation methodologies

§  Develop CAD Methodology Roadmap in support of future business unit product development requirements

§  Develop and implement custom cell characterization and timing flow using SiliconSmart and PrimeTime

Functional Verification Manager

§  Design and implement self-checking fullchip verification testbench for DDR/DDR2/DDR3 DRAM products using Verilog and SystemVerilog

§  Implement environment using Perl, DesignSync, and LSF to manage large numbers of simulation jobs

 

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§  Provide regular Verilog and simulation environment training to design engineers at various company locations

 

§  Manage team of verification development and applications engineers at various international sites

1996-2002    Level One Communications/Intel Corp.                                           Sacramento, CA

                     Staff Component Design Engineer

§  Lead cross-functional engineering team responsible for analog/digital simulation methodology and testbench development

§  Write and support Verilog analog behavioral models for 1G/100M/10M Ethernet Phy design

                     Physical Design Tools Supervisor

§  Responsible for the integration and support of all back-end physical design tools including Hercules DRC/LVS, STAR-RC, Apollo APR, Virtuoso Layout, and CATS Maskview

§  Develop and support custom Hercules DRC/LVS and STAR-RC runsets for 0.6um, 0.35um, 0.25um, and 0.18um process nodes – TSMC/Chartered/UMC Common Runsets

§  Provide foundry interface services during design and tapeout of over 20 products

1990-1996    Micron Technology, Inc.                                                                  Boise, ID      

                     CAD Engineer/Product Engineer

§  Convert physical verification tools from Edge pdv and Cadence DIVA to Hercules

§  Development and implement custom interface for physical verification tools

Education

1985-1990      BS Electrical Engineering, Graduated with High Scholarship

                     Oregon State University, Corvallis, Oregon